Architecture IA-64 and processor Merced

Company Intel in cooperation with Hewlett-Packard plans radical architectural innovations in the future 64-digit processor developed under code name Merced. Architecture Merced has received name IA-64 (Intel Architecture-64), and she back is compatible with the command system as 32-bit architecture х86 companies Intel (see Family of MT х88/х86), and 64-digit architecture PA-RISC of company Hewlett-Packard. Architecture Merced will not concern to CISC-architecture (Complex Instruction Command Set), to RISC-architecture (Reduced Instruction Command Set) as, in opinion Intel and Hewlett-Packard, they have exhausted(settled) limits of the growth. In IA-64 the new encoder of VLIW commands will be used (Very Long Instruction Words), in which commands of the processor are packed on three into a 128-bit package for faster processing. Commands have the fixed length and do not require use of a microcode in the processor. Besides each of words VLIW contains the information (placed in him(it) the compiler) about an opportunity of parallel execution(performance) of prisoners in him of commands. Therefore the processor can not analyze a stream of commands for revealing the latent parallelism — this duty is assigned to the compiler as at a stage of compilation the information on parallelism is more authentic. Processors of architecture IA-64 will contain 128 integer registers and 128 registers for calculations with a floating point, and all of them will be accessible to the programmer as registers with random access. A plenty of registers will essentially increase uniformity of loading of the conveyor of the processor. Besides in IA-64 additional measures on a prediction of transitions and on maintenance of preliminary loading the data are undertaken. Architecture IA-64 means, that the most part of job on optimization of a code of the program will be carried out by the compiler. { Intel}

The first processor of architecture IA-64, Merced, is developed for servers and workstations of a class high-end. He will be established in new socket Slot M. His(its) occurrences should be expected till 2000. According to plans Intel, in the near future Merced will not replace х86, and any time both architecture will develop in parallel.

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